Description: Verilog编写的异步串行FIFO程序,包括各种标志位,指针注释,其中还有SDRAM的读写程序-Asynchronous serial FIFO write Verilog procedures, including a variety of flag, pointer annotations, among them a SDRAM read and write procedures for Platform: |
Size: 3988480 |
Author:张跃平 |
Hits:
Description: 同步FIFO和异步FIFO程序,希望对大家有用!verilog程序。-Synchronous FIFO and asynchronous FIFO procedures, and hope to be useful! The verilog procedure. Platform: |
Size: 5120 |
Author:dean |
Hits:
Description: verilog语言时序的异步读写FIFO,请需要者借鉴参考-the verilog language Timing asynchronous read and write FIFO, for those who need to learn from reference Platform: |
Size: 185344 |
Author:张炽 |
Hits:
Description: 使用verilog语言编写的异步串口模块,带有16级深的FIFO,它与DSP28335的SCI相似,可以帮助初学者更快地理解FPGA和DSP的硬件结构和编程思路-Use verilog language of asynchronous serial port module, FIFO with deep level 16, it was similar with DSP28335 SCI, can help beginners to understand faster the FPGA and DSP hardware structure and programming ideas Platform: |
Size: 492544 |
Author:夏小保 |
Hits:
Description: 异步fifo 先进先出 用于缓冲数据,用verilog HDL所写,在quartus II中测试通过,modelsim仿真-Asynchronous fifo FIFO for buffering data, using verilog HDL written in quartus II test through, modelsim simulation Platform: |
Size: 4096 |
Author:T~T |
Hits:
Description:
本文同步FIFO为TPRAM(两端口RAM,一读一写)。有详细verilog 程序以及说明-FIFO divided by clock domain can be divided into synchronous and asynchronous FIFO FIFO, FIFO read and write only one clock synchronous, asynchronous FIFO read and write were a clock. FIFO divided by port can be divided into TPRAM, DPRAM, TPRAM read one each port, a port read-only, write-only another port, DPRAM read each one each port, each port can either be read. This article synchronous FIFO is TPRAM (two-port RAM, a read a write). Platform: |
Size: 650240 |
Author:jodyql |
Hits:
Description: Verilog语言写的异步fifo,包含随机数产生电路和testbentch,直接可用于实际工程中。代码为华为内部代码。相信你会喜欢。-Verilog language used to write asynchronous fifo, including random number generation circuit and testbentch, can be used directly in the actual project. Code for Huawei internal code. I believe you will like it. Platform: |
Size: 27829248 |
Author:allcot |
Hits:
Description: 异步fifo用verilog语言实现的完整代码,适用于数字前端的设计-This implementation is based on the article Asynchronous FIFO Platform: |
Size: 1024 |
Author:张牡丹 |
Hits:
Description: 给出一个位宽16比特,深度为10的异步FIFO的设计,并要求给出空或满的指示信号。要求用Verilog HDL语言设计,并编写测试激励,以及用Modelsim进行功能仿真,验证设计正确性。10个16位的数据 (FIFO的宽度:也就是英文资料里常看到的THE WIDTH,它指的是FIFO一次读写操作的数据位,就像MCU有8位和16位,ARM 32位等等。FIFO的深度:THE DEEPTH,它指的是FIFO可以存储多少个N位的数据(如果宽度为N)。如一个8位的FIFO,若深度为8,它可以存储8个8位的数据,深度为12,就可以存储12个8位的数据。)-Give a 16 bits wide, depth of 10 asynchronous FIFO design, and requires giving empty or full instructions signal. Request using Verilog HDL language design, and the writing test, and simulation using Modelsim function, validate design is correct. 10 16 bits of data (THE WIDTH of THE FIFO, namely information in English often see THE WIDTH, it refers to a FIFO data read and write operations, as has 8 bit or 16 bit MCU, ARM 32-bit and so on. THE depth of FIFO: THE DEEPTH, it refers to THE FIFO can store many N bits of data (if THE WIDTH is N). If an 8-bit FIFO, if THE depth of 8, it can store 8 8 bits of data, THE depth of 12, 12 8 bits of data to be stored.) Platform: |
Size: 33792 |
Author:江燕子 |
Hits:
Description: 用verilog编写的简单异步fifo。可以给初学者用来学习fifo的初步工作原理。(不能直接使用。)-Verilog prepared by the simple asynchronous fifo. Can be used for beginners to learn fifo the initial working principle. (Can not be used directly.) Platform: |
Size: 1024 |
Author:刘宇洋 |
Hits: